1. Field
The disclosure relates generally to a voltage regulator and, more particularly, to output power management thereof.
2. Description of the Related Art
Voltage regulation is important where circuits are sensitive to transients, noise and other types of disturbances. The control of the regulated voltage over variations in both semiconductor process variation, and temperature is key to many applications. Additionally, power consumption is also a key design requirement.
In recent PMIC, precise output monitoring of buck is required for more efficient power management of processors. Sensed and digitized average output current information is used for controlling processors.
FIG. 1 shows the circuit schematic in a block diagram form of the prior art. The buck circuit 100 comprises a pulse width modulation (PWM) control unit 105, an output stage 130, a current sensing network 120, a buffer 140, and an analog-digital converter (ADC) 150. The output stage 130 comprises a p-channel MOS (PMOS) pull-up 135, and n-channel MOS (NMOS) pull-down 145. The sensing network is shown for the case of the NMOS 145 sense.
The current sense network 120 has a pull-up Sense NMOS 160, and pull-down Sense NMOS 165 whose signal is inverted by inverter 162. The output signal is connected to a Sampling switch SW 170 which receives a switch signal from the PWM controller 105. The Sampling switch SW is connected to an RC filter comprising resistor R 172 and capacitor C 175. A comparator 180 receives a signal to its negative input, an produces a negative polarity denoted as −Isense signal 182 which is a feedback loop to the input of the Sampling switch SW 170 and Isense signal, 184.
The output stage 130 has a center node LX 136 which is connected to the LC filter formed from inductor 152 and capacitor 153, for the output node voltage vout 155.
The output current causes the voltage drop over NMOS 145 during NMOS is turned on. The current sense amp converts the voltage drop into the sense current Isense. Isense is translated into voltage with Riv and digitized by ADC. Thus the digitized and averaged output current information is obtained.
As discussed, the Current sense amp 120 is comprised of sense NMOS 160, sampling switch 170, RC low pass filter (LPF) comprising resistor R 172 and capacitor C 175 and output trans-conductance amplifier OTA 180.
FIG. 2 is a timing diagram of the current sense amplifier 200 for the prior art embodiment shown in FIG. 1. The timing diagram 200 illustrates the Inductor current ILX 210, voltage v(LX) 220, and sample voltage Vsample_in 230, and OTA voltage Vota_inn 240. The sensed voltage Vsense during NMOS 160 on-time is expressed using the NMOS 145 on-resistance Rnon and the sense NMOS's 160 on-resistance Rsense:Vsense=−Rnon*ILX+Rsense*Isense
Vsense is sampled during the NMOS 145 on time and held during the off time, and inputted to the OTA through RC low pass filter (LPF). The OTA controls Isense so that average of Vinn is equal to zero or ground level. If average of Vinn is equal to average of Vsense, average of Isense is proportional to average of ILX.Average(Isense)=(Rnon/Rsense)*average(ILX)
But in reality, Vsense swings with ripple of the output current during the NMOS is turned on. As a result, the voltage Vinn held by the Sampling switch SW 170 at the end of the NMOS on time is shifted from average of Vsense and it causes error of the output current monitor.
U.S. Pat. No. 8,508,203 to Tang et al., describes a control logic circuit, for receiving a pulse width modulation (PWM) signal and a confirmation signal, and generating a setting signal, a resetting signal, and a lower gate control signal; a level shift circuit, coupled to the control logic circuit, for converting the setting signal and the resetting signal.
U.S. Pat. No. 5,955,871 to Nguyen, describes a switching regulator for use with a computer system having a power conservation mode includes a switch circuit, a sampling storage device, a sampling circuit and a controller.
U. S. Patent Application 20100033146 to Irissou et al., describes a method for providing output (e.g., current) sensing and feedback in switching power converter topologies. Some embodiments include feedback functionality for generating a converter driver signal (for driving the switching converter) and/or a sample driver signal (for driving the sampling module) as a function of sensed output feedback from the sampling module
WO 1999031790 to Clark et al., describes a regulator with a sampling circuit that makes measurements of an electrical characteristic of the voltage regulator at discrete moments of time. A feedback circuit is coupled to the sampling circuit and the switch, and is configured to use the measurements to control the duty cycle to maintain the DC voltage substantially constant.
In these prior art embodiments, the solution to establish sensing schemes for improved operation utilized various alternative solutions.